1. Field of the Invention
The invention relates to computer-aided design systems, and in particular to computer aided electronic design systems which facilitate the design, simulation and layout of integrated circuit chips.
2. Related Art
Integrated circuit technology has provided a basis for the design of increasingly miniaturized systems, often providing capabilities impossible orimpractical on a larger scale. As technology has progressed, the need for greater density of integrated circuit technology. As the geometries of integrated circuit devices shrink and the capability to provide more function on a single integrated circuit grows, the need arises to provide designers with tools to facilitate the design of more complicated integrated circuit chips. This capability is provided by computer aided design systems.
Integrated circuits are often designed by the designer in a modular fashion. The designer breaks up the design into small, manageable pieces and captures each such piece as a module. A completed design may comprise many such modules, and modules may further comprise other modules, etc. This xe2x80x9cnestedxe2x80x9d modular approach is particularly useful when a design is highly repetitive, since a relatively simple module may be designed and debugged, then replicated many times. This allows both a high degree of confidence in the finished design and a relatively low level of effort required to complete it. Computer-aided design systems, hereinafter referred to as CAD systems, are well known in the present art. Such systems are in wide use in a number of engineering disciplines for the purpose of facilitating the design of such things as: electronic circuits and circuit boards (electronic CAD, or ECAD systems), mechanical systems (mechanical CAD, or MCAD systems), software (computer-aided software engineering, or CASE), and integrated circuits (also known as ECAD systems). Of particular relevance to the present invention are those ECAD systems used to design, simulate and layout integrated circuit chips and circuit boards comprising a number of discrete chips.
ECAD systems of this type have been in use for many years. Specific examples of such systems include ECAD systems provided by Mentor Graphics, Inc. of Beaverton, Oreg., Valid Logic Systems of Mountain View, Calif., and LSI Logic Corporation of Milpitas, Calif., among others. In all cases, these ECAD systems comprise a set of software tools running on a computer-based workstation. Typically, such tools include a schematic editor, a circuit compiler, a linker, a simulator, and layout tools. The normal flow of operation is xe2x80x9cserialxe2x80x9d in that the designer runs the schematic editor to create a design, which is stored in a design dataset. Then the designer exits the editor and runs a compiler which processes the design dataset producing another design dataset. This is then xe2x80x9clinkedxe2x80x9d which produces yet another design dataset, and so on.
An example of such software tools is given by the MDE (Modular Design Environment) system produced by LSI Logic Corp. of Milpitas, Calif. This system runs on a Sun Microsystems workstation, running the UNIX operating system and the SUNVIEW windowed graphical user interface, and includes a schematic editor (LSED), compiler, linker, logic simulator (LSIM), layout editor, bonding editor, floorplanning utility, and design rule checker.
Designers spend most of their integrated circuit design time engaged in a process which has become known as an xe2x80x9cedit-compile-simulatexe2x80x9d loop. This process involves creating and/or modifying one or more schematic diagrams with a schematic editor, compiling and linking the newly entered/modified design, and then running a simulator to determine whether or not the new design will perform as expected. If not, as is often the case, or if there are some enhancements or improvements to be made, the designer will return to the start of the process; re-editing, re-compiling and re-simulating repetitively until he is satisfied that the design performs as expected.
Another reason designers spend a great deal of time in the xe2x80x9cedit-compile-simulatexe2x80x9d loop is that many designers will test a design incrementally as it is created by simulating any previously design work along with some new design work. In this manner, confidence in the design is established in small steps, requiring a great deal less effort and insight at any given time than trying to test (and debug) a large design all at once. A designer or group of designers may make many cycles through this process before completing a design.
Because of the repetitive nature of the design actions taken in creating an integrated circuit design, any reduction in the amount of time required to perform any of these repeated steps will reduce the total design time by an amount as many times greater than the time savings as the number of cycles through the edit-compile-simulate process experienced by the designer.
A weakness in many present ECAD systems is that the design process is divided into two relatively isolated processes: design and layout. The design part of the process involves schematic capture, compilation, and linking; while the layout part involves layout floorplanning, component placement, signal routing, analysis of the layout for parameters such as parasitic capacitance, and back-annotation of the original design with information derived during the layout process. After the layout, the designer will likely re-simulate for the purpose of locating any layout-induced problems. If there are any problems, the edit-compile-simulate process will be repeated, this time extending the process to include layout. Because of the relative isolation of the layout process from the rest of the design process, layout is also performed serially, often being performed using software tools (programs) having user interfaces which bear little or no resemblance to those of the software tools used during the design process. An example of a floorplanner is found in commonly-owned U.S. Pat. No. 4,918,614, entitled HIERARCHICAL FLOORPLANNER, issued on Apr. 17, 1990 to Modarres, Raam and Lai.
Much of the design process is repetitive or predictable. The designer makes changes to a circuit design, then compiles, links, simulates, etc. This process usually requires the designer to run the same programs and provide them with the same or similar inputs over and over. This process of manually running programs and re-entering input parameters, re-executing processes which have already been performed before and which have already provided much the same results, etc., can be quite time-consuming.
Accordingly, it is desirable to provide design tools which remove from the designer the task of manually running iterative simulations to achieve an acceptable circuit design.
An electronic computer aided design system provides for automated operation of a plurality of design tools to produce multiple design solutions to an initial circuit layout. Through the user entry of relative weights for: power, timing and area, different solutions to an initial layout can be generated exhibiting the requested balance of improvements over the original layout. A novel parts placement apparatus and process is disclosed which prioritizes the reconfiguration of the initial design in a manner which assures that the multiple solutions will be generated which exhibit improved performance over the original layout in accordance with the priorities established by the user. A novel compaction apparatus and method is disclosed. A method and apparatus for generating multiple solutions to an initial electronic layout of cells is disclosed. The method for generating multiple solutions comprises:
locating critical paths in the initial layout and each critical path containing line segments joining adjacent cells which are saturated;
defining a cut list including critical cuts and each of the critical cuts severing the critical paths located in said act of locating, and each critical cut including at least one cell from each of the critical paths; and
removing and replacing the at least one cell associated with selected critical cuts to produce a solution list including solutions to the initial electronic layout, and the solutions differing from the initial layout in the relative placement of the cells.
In another embodiment of the invention, an apparatus for generating multiple solutions is disclosed which comprises:
means for locating critical paths in the initial layout and each critical path containing line segments joining adjacent cells which are saturated;
means for defining a cut list including critical cuts and each of the critical cuts severing the critical paths located in said act of locating, and each critical cut including at least one cell from each of the critical paths; and
means for removing and replacing the at least one cell associated with selected critical cuts to produce a solution list including solutions to the initial electronic layout, and the solutions differing from the initial layout in the relative placement of the cells.
In another embodiment of the invention a computer usable medium having computer readable program code means embodied therein for compacting an initial electronic layout of cells within an initial layout boundary is disclosed. The initial layout boundary includes opposing bottom and top edges; and the computer readable program code means in said article of manufacture comprises:
computer readable program code means for forming paths extending from the bottom edge to the top edge and the paths intersecting cells of the initial layout, and the paths each including line segments linking a lower cell to an upper cell;
computer readable program code means for determining which of the paths are critical paths, each critical path containing line segments all of which are saturated;
computer readable program code means for removing cells of the initial layout associated with the critical paths determined during said act of determining; and
computer readable program code means for replacing the cells removed during said act of removing, into the initial layout boundary in a location which allows the initial layout boundary to be reduced in a dimension.